This patent relates to a semiconductor device. More specifically, this patent relates to a semiconductor device having a dummy pattern and a method for fabricating the semiconductor device which are capable of preventing defects caused by lifting of a dummy pattern.
A recent trend toward high-integration semiconductor devices, e.g., dynamic random access memories (DRAMs) has brought about a reduction in size of design rule and a decrease in fabrication margin. Accordingly, based on fine processing applied to a semiconductor substrate, a great number of patterns are being formed within the limited area of the semiconductor substrate. During the formation of the great number of patterns on the semiconductor substrate, there arises a difference in level (hereinafter, it is referred to as a “step”) among the patterns formed on the substrate.
Meanwhile, such a step may be more readily formed in a pattern dense region, as compared to a pattern loose region. More specifically, the thickness of the film deposited in the pattern dense region is relatively larger than that of the pattern loose region, thus creating a step between the regions. An excessive step between the regions causes deterioration of device characteristics. Accordingly, there are used a variety of methods in an attempt to offset the step prior to the following process. Of these methods, there is a method for introducing a dummy pattern into the pattern dense region.
FIGS. 1 to 3 are views illustrating conventional dummy patterns. FIGS. 2 and 3 are cross-sectional views taken along the line A-A′ and the B-B′ of FIG. 1, respectively.
Referring to FIGS. 1 to 3, an etching stop film 102 is arranged on a semiconductor substrate 100 where underlying structures including word lines and lit lines are formed. An interlayer dielectric film 104 is arranged on the etching stop film 102. A wire layer 106 is arranged on the interlayer dielectric film 104. There is a difference in density of the wire layer 106 between adjacent regions. A contact plug 108 is arranged in the interlayer dielectric film 104. The contact plug 108 connects the underlying structures arranged on the semiconductor substrate to the wire layer 106. Each dummy pattern 110 reduces the step between the regions having different pattern densities.
The dummy pattern 110 reducing the step is attached to the surface of the interlayer dielectric film 104. During cleaning and heating, after photolithography, there occur defects, e.g., lifting or detachment of the dummy pattern 110. To prevent the occurrence of the defects, there has been suggested a decrease in the size of the dummy pattern 110. The decrease in the size of the dummy pattern 110 makes it impossible to reduce the step to the desired level and causes deterioration of device characteristics resulted from the dummy pattern defects such as lifting or detachment.